A low latency and low power indirect topology for on-chip communication
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Usman Ali Gulzari aff001; Sarzamin Khan aff002; Muhammad Sajid aff003; Sheraz Anjum aff004; Frank Sill Torres aff005; Hessam Sarjoughian aff006; Abdullah Gani aff007
Působiště autorů:
Department of Electrical Engineering, The University of Lahore, Islamabad, Pakistan
aff001; Department of Electrical Engineering, COMSATS University Islamabad, Wah Campus, Wah Cantt, Pakistan
aff002; Department of Electrical and Computer Engineering, University of Western Ontario, London, Ontario, Canada
aff003; Department of Computer Science, COMSATS University, Islamabad, Wah Campus, Wah Cantt, Pakistan
aff004; German Aerospace Center, Institute for the Protection of Maritime Infrastructures, Bremerhaven, Germany
aff005; Arizona Center for Integrative Modeling & Simulation, Arizona State University, Tempe, United States of America
aff006; Faculty of Computing and Informatics, Universiti Malaysia Sabah, International Campus Labuan, WP Labuan, Malaysia
aff007
Vyšlo v časopise:
PLoS ONE 14(10)
Kategorie:
Research Article
doi:
https://doi.org/10.1371/journal.pone.0222759
Souhrn
This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively.
Klíčová slova:
Algorithms – Energy transfer – Intelligence – Memory – Network analysis – Telecommunications – Network bandwidth – Moths and butterflies
Zdroje
1. Khawaja SG, Mushtaq MH, Khan SA, Akram MU, ullah Jamal H. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees. PloS one. 2015 Apr 21;10(4):e0125230. doi: 10.1371/journal.pone.0125230 25898016
2. Khan S, Anjum S, Gulzari UA, Torres FS. Comparative analysis of network-on-chip simulation tools. IET Computers & Digital Techniques. 2017 Sep 25;12(1):30–8.
3. Muhammad ST, Ezz-Eldin R, El-Moursy MA, Refaat AM. Low-Power NoC Using Optimum Adaptation. In Computational Intelligence in Digital and Network Designs and Applications 2015 (pp. 191–221). Springer, Cham.
4. Khan S, Anjum S, Gulzari UA, Umer T, Kim BS. Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture. IEEE Access. 2017 Nov 29;6:11242–54.
5. PD SM, Lin J, Zhu S, Yin Y, Liu X, Huang X, et al. A scalable network-on-chip microprocessor with 2.5 D integrated memory and accelerator. IEEE Transactions on Circuits and Systems I: Regular Papers. 2017 May 19;64(6):1432–43.
6. Ju X, Yang L. Performance analysis and comparison of 2× 4 network on chip topology. Microprocessors and Microsystems. 2012 Aug 1;36(6):505–9.
7. Gulzari UA, Anjum S, Agha S. Cross by pass-mesh architecture for on-chip communication. In2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip 2015 Sep 23 (pp. 267–274). IEEE.
8. Kumar S, Norige E, Raponi PG, inventors; NetSpeed Systems, assignee. Systems and methods for selecting a router to connect a bridge in the network on chip (NoC). United States patent US 9,762,474. 2017 Sep 12.
9. Khan Z, Alam M, Haidri RA, Effective Load Balance Scheduling Schemes for Heterogeneous Distributed System. International Journal of Electrical and Computer Engineering (IJECE) 7(5), 2757–2765 (2017).
10. Ahmadi A, Shojafar M, Hajeforosh SF, Dehghan M, Singhal M. An efficient routing algorithm to preserve-coverage in wireless sensor networs. The Journal of Supercomputing. 2014 May 1;68(2):599–623.
11. Qasem MF, Gu H. Square-octagon interconnection architecture for network-on-chips. In2014 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC) 2014 Aug 5 (pp. 715–719). IEEE.
12. Anjum S, Khan IA, Anwar W, Munir EU, Nazir B. A Scalable and Minimized Butterfly Fat Tree (SMBFT) Switching Network for On-Chip Communication. Research Journal of Applied Sciences, Engineering and Technology. 2012 Jul 1;4(13):1997–2002.
13. Sahu PK, Manna K, Shah N, Chattopadhyay S. Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip. Journal of Systems Architecture. 2014 Aug 1;60(7):562–78.
14. Hossain H, Akbar M, Islam M. Extended-butterfly fat tree interconnection (EFTI) architecture for network on chip. InPACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005. 2005 Aug 24 (pp. 613–616). IEEE.
15. Hossain H, Ahmed M, Al-Nayeem A, Islam TZ, Akbar MM. Gpnocsim-a general purpose simulator for network-on-chip. In2007 International Conference on Information and Communication Technology 2007 Mar 7 (pp. 254–257). IEEE.
16. Kahng AB, Lin B, Nath S. ORION3. 0: a comprehensive NoC router estimation tool. IEEE Embedded Systems Letters. 2015 Feb 10;7(2):41–5.
17. Tran AT, Baas B. NoCTweak: a highly parameterizable simulator for early exploration of performance and energy of networks on-chip. VLSI Computation Lab, ECE Department, University of California, Davis, Tech. Rep. ECE-VCL-2012-2. 2012 Jul.
18. Gulzari UA, Anjum S, Aghaa S, Khan S, Torres FS. Efficient and scalable cross-by-pass-mesh topology for networks-on-chip. IET Computers & Digital Techniques. 2017 Feb 3;11(4):140–8.
19. Gulzari UA, Sajid M, Anjum S, Agha S, Torres FS. A new cross-by-pass-torus architecture based on CBP-mesh and torus interconnection for on-chip communication. PloS one. 2016 Dec 1;11(12):e0167590. doi: 10.1371/journal.pone.0167590 27907147
20. Chen C, Meng J, Coskun AK, Joshi A. Express virtual channels with taps (evc-t): A flow control technique for network-on-chip (noc) in manycore systems. In2011 IEEE 19th Annual Symposium on High Performance Interconnects 2011 Aug 24 (pp. 1–10). IEEE.
21. Grot B, Hestness J, Keckler SW, Mutlu O. Express cube topologies for on-chip interconnects. In2009 IEEE 15th International Symposium on High Performance Computer Architecture 2009 Feb 14 (pp. 163–174). IEEE.
22. Kim J, Balfour J, Dally W. Flattened butterfly topology for on-chip networks. InProceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture 2007 Dec 1 (pp. 172–182). IEEE Computer Society.
23. Chen CH, Agarwal N, Krishna T, Koo KH, Peh LS, Saraswat KC. Physical vs. virtual express topologies with low-swing links for future many-core nocs. In2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip 2010 May 3 (pp. 173–180). IEEE.
24. Ngo VD, Nguyen HN, Choi HW. Analyzing the performance of mesh and fat-tree topologies for network on chip design. InInternational Conference on Embedded and Ubiquitous Computing 2005 Dec 6 (pp. 300–310). Springer, Berlin, Heidelberg.
25. Elmiligi H, Morgan AA, El-Kharashi MW, Gebali F. Power optimization for application-specific networks-on-chips: A topology-based approach. Microprocessors and Microsystems. 2009 Aug 1;33(5–6):343–55.
26. Morgan AA. Networks-on-chip: modeling, system-level abstraction, and application-specific architecture customization (Doctoral dissertation).
27. Sahu PK, Sharma A, Chattopadhyay S. Application mapping onto mesh-of-tree based network-on-chip using discrete particle swarm optimization. In2012 International Symposium on Electronic System Design (ISED) 2012 Dec 19 (pp. 172–176). IEEE.
28. Flich J, Duato J. Logic-based distributed routing for NoCs. IEEE Computer Architecture Letters. 2008 May 30;7(1):13–6.
29. Anjum S, Chen J, Yue PP, Liu J. Delay optimized architecture for on-chip communication. Journal of Electronic Science and Technology. 2009 Jun;7(2):104–9.
30. Pande PP, Grecu C, Jones M, Ivanov A, Saleh R. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE transactions on Computers. 2005 Jun 20;54(8):1025–40.
31. Raju TN. William Sealy Gosset and William A. Silverman: two “students” of science. Pediatrics. 2005 Sep 1;116(3):732–5. doi: 10.1542/peds.2005-1134 16140715
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